Stability Analysis of PLL on DFIG-WT with Frequency Support Capability and Robust Damping Controller Design

Abstract

Phase-locked loop (PLL) is designed to estimate the frequency and phase angle of grid voltage. When a PLL is used to measure the point of common coupling frequency during DFIG-WTs participating in system frequency support, a new oscillation mode will be excited and dominated by both a PLL and an inertia emulation controller. Analysis results are provided to show that the weak power grid and large PLL parameters will deteriorate the system stability when DFIG-WTs participate in the system frequency support. A multi-objective H <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> /H <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∞</inf> synthesis based damping controller is proposed which can ensure robust system stability against parameters uncertainties and time-varying system operating points. Small signal stability analysis and simulation results are obtained which indicates the PLL and inertia emulation controller dominated oscillation can be mitigated within 10s with the designed robust damping controller.