Abstract
A problem inherent in power-gated circuits is the overhead of state-retention storage required to preserve the circuit state in standby mode. <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HLS</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pg</i> is a new design framework that takes power gating into account, from scheduling, allocation, and controller synthesis to the final circuit layout. Its main feature is a new scheduler that minimizes the number of retention registers required at the power-gating control step. In experiments on benchmark designs implemented in 0.9-V 65-nm technology, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HLS</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pg</i> reduced leakage current by 20.7% on average, with 5.0% less area and 4.1% less wirelength, compared to the power-gated circuits produced by conventional high-level synthesis.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.