SRAM/TEG Yield Methodology

Abstract

Yield growth over a process life determines the slope of the learning curve that a given process will follow. It can be easily shown that modest differences in the slope of the learning curve can determine the survival of a product or perhaps even a whole facility [1]. The relatively low volume per design and potential large number of designs incurred by a custom circuit foundry, coupled with the complexities of VLSI technology present an extremely complicated yield enhancement problem. A large part of this is the ability to identify defect sources and reduce or eliminate them in a timely fashion. This requires a diligent effort during lot processing to minimize defect sources as well as after lot completion in post process failure analysis. Unfortunately, as the minimum feature size of custom circuits passes through the micron regime and chip sizes exceed 100mm 2, containing 106 or more transistors, many of the standard yield enhancement practices lose effectiveness. Due to the reduced circuit dimensions and increased pattern complexity it becomes highly probable that manual in-process inspection will not detect defects. This is particularly true in a custom house where the circuit pattern is more random and continually changing with mask sets removing the aid of familiarity from the inspector. Post-process failure analysis also suffers because with the greater number of components and functions per chip extremely large vector sets must be run to isolate circuit failures. As well as increasing the test time, the time required for data analysis to correlate the electrical failure with physical circuit location is also significantly increased. The effectiveness of yield enhancement efforts in both of these areas for VLSI technology can be reinstated through the use of a SRAM/TEG yield vehicle. The SRAM/TEG combines a static random access memory (SRAM) with a test element group (TEG) on a single chip providing a unified process control vehicle. Due to the repetitiveness and regularity of its high density pattern the SRAM is an effective in-process inspection vehicle even at the micron level. A one to one correspondence of bit map and SRAM cell location provides an easy method of testing for defects and decoding defect location at post process failure analysis. Parametric and yield structures in the test element group supplement the SRAM nicely in failure mechanism identification.