Abstract
In-memory computing (IMC) SRAM has been demonstrated as a promising technique to significantly improve energy-efficiency for deep neural network (DNN) hardware accelerators. However, designing one involves setting many design variables such as the number of parallel rows to simultaneously activate, analog-to-digital converter (ADC) resolution at the periphery of a memory sub-array, precisions of various parts of a DNN model, etc., which affect energy-efficiency, accuracy, and area. Prior works have not investigated this multi-dimensional design optimization. To fill this knowledge gap, we present an SRAM-based IMC hardware modeling and optimization framework. https://underline.io/speakers/60043-jae-sun-seo
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