SRAM read-assist scheme for high performanc low power applications

Abstract

In nanoscale CMOS technologies, SRAMs employ aggressively small cells, which makes them extremely vulnerable to process variation, degrading the worst case cell read current and threatening the reliability of sensing scheme. The increased effect of process variation in nanoscale technologies, along with continuous increase in the size of SRAMs, requires additional techniques and treatment such as read-assist techniques to ensure fast and reliable read operation. A read-assist circuit in 65nm CMOS technology is proposed in this paper which reduces the access time significantly and enhances SRAM cell stability. A complete comparison is made between the proposed scheme, conventional circuit and another state of the art design which shows speed improvement and power reduction of 55.3% and 21.3%, over conventional circuit respectively. Furthermore, in order to have the same sensing speed, the proposed scheme enables us to reduce cell V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> by 227mV which results in considerable reduction in leakage power dissipation.