Abstract
Subsampling fractional PLLs (SSPLL) offer better in-band phase noise performance than other conventional PLLs. However, the issue of spurs is persistent like in every other PLL. The causes of spurs in SSPLLs are phase difference errors between the oscillator phases, shape of the oscillator waveform, fractional frequency divider delay and phase-frequency detector and charge pump nonidealities. In this article, the causes of spurs are modeled and compared with simulated values which match with fair accuracy. Additionally, a SSPLL is designed with a control voltage sampler to reduce spurs due to phase errors that may arise due to process variations and device mismatches. The addition of the sampler helps in reducing the fractional spurs from $$-46$$ / $$-53$$ dBc to $$-50$$ / $$-61$$ dBc in the worst and best circuit conditions. The SSPLLs are analyzed and designed in 180 nm CMOS technology.
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