Abstract
Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split $C$ – $V$ measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the $RC$ response of the channel in regular, large-area ones, making the extraction in standard samples problematic.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
