Spike-Timing-Dependent-Plasticity with Memristors

Abstract

(This chapter is reprints material from Zamarreno-Ramos et al. in Front. Neurosci. 5:26, 2011 and Serrano-Gotarredona et al. in Front. Neurosci. 7:02, 2013, with permission.) Here we present a very exciting overlap between emergent nano technology and neuroscience, which has been discovered by neuromorphic engineers. Specifically, we are linking one type of memristor nano technology devices to the biological synaptic update rule known as Spike-Time-Dependent-Plasticity found in real biological synapses. Understanding this link allows neuromorphic engineers to develop circuit architectures that use this type of memristors to artificially emulate parts of the visual cortex. We focus on the type of memristors referred to as voltage or flux driven memristors and focus our discussions on behavioral macro models for such devices. The implementations result in fully asynchronous architectures with neurons sending their action potentials not only forwards but also backwards. One critical aspect is to use neurons that generate spikes of specific shapes. We will see how by changing the shapes of the neuron action potential spikes we can tune and manipulate the STDP learning rules for both excitatory and inhibitory synapses. We will see how neurons and memristors can be interconnected to achieve large scale spiking learning systems, that follow a type of multiplicative STDP learning rule. We will briefly extend the architectures to use three-terminal transistors with similar memristive behavior. We will illustrate how a V1 visual cortex layer can be assembled and how it is capable of learning to extract orientations from visual data coming from a real artificial CMOS spiking retina observing real life scenes. Finally, we will discuss limitations of currently available memristors. The results presented are based on behavioral simulations and do not take into account non-idealities of devices and interconnects. The aim here is to present, in a tutorial manner, an initial framework for the possible development of fully asynchronous STDP learning neuromorphic architectures exploiting two or three terminal memristive type devices. (A Supplemental Material compressed zip file containing all files used for the simulations can be downloaded from http://www.frontiersin.org/neuromorphic_engineering/10.3389/fnins.2011.00026/abstract.)