SPIHT image compression on FPGAs

Abstract

In this paper, we present an implementation of the image compression routine set partitioning in hierarchical trees (SPIHT) in reconfigurable logic. A discussion on why adaptive logic is required, as opposed to an application specific integrated circuit (ASIC), is provided along with background material on the image compression algorithm. We analyzed several discrete wavelet transform (DWT) architectures and selected the folded DWT design. In addition we provide a study on what storage elements are required for each wavelet coefficient. A modification to the original SPIHT algorithm is implemented to parallelize the computation. The architecture of our SPIHT engine is based upon fixed-order SPIHT, developed specifically for use within adaptive hardware. For an N/spl times/N image fixed-order SPIHT may be calculated in N/sup 2//4 cycles. Square images which are powers of 2 up to 1024/spl times/1024 are supported by the architecture. Our system was developed on an Annapolis Microsystems WildStar board populated with Xilinx Virtex-E parts. The system achieves a 450/spl times/ speedup versus a microprocessor solution, with less than a 0.2-db loss in peak signal-to-noise ratio over traditional SPIHT.