SPICE implementation of a compact single electron tunneling transistor model

Abstract

A novel compact single electron tunneling transistor (SETT) SPICE model is described in this paper. This SPICE implementation is based on an analytical model derived from a simplified full master equation model. Besides of being able to accurately capture the SETT behavior under various circuit and temperature conditions our proposal can also evaluate background charge effects in SETT circuits. This is achieved by associating random seeds that model the random background charge noise effect to each SETT in the circuit. To validate our proposal we simulated with the proposed model, as well as with other more computationally demanding models, an inverter, a ring oscillator, and a hybrid SETT/MOSFET circuit. The simulation results clearly indicate that our model provides the same accuracy as other state-of-the-art SETT SPICE models. However, due to the simplicity of the compact current model we use our proposal can save on simulation time and this makes it potentially applicable for large-scale circuit simulation.