Speedup of lock up time in the PLL frequency synthesizer using frequency detector

Abstract

In this paper, we propose a new speedup method of the lock up time in the Phase Locked Loop (PLL) frequency synthesizer which is used in the automatic tuning instruments of radio receivers. When a division ratio of the programmable divider is changed, the PLL frequency synthesizer shows the transient response of a second order system. Therefore, the PLL frequency synthesizer cannot help having a slow lock up time. For an improvement of the lock up time, first, in order to find objective frequency, we propose a new frequency detector (FD) which detects only the frequency agreement between the reference frequency fr and feedback one fv. Once the frequency agreement is detected, the reference divider and programmable divider are reset and the phase between the reference frequency fr and feedback one fv is forced to be locked. Moreover, the input of charge pump is kept in the same state by a Charge Controller (CC) during the change of the division ratio resulting in the frequency agreement. As a result, the speedup of lock up time can be achieved by adopting the FD and CC at the same time.