Abstract
A detailed model is presented for the speed-up of parallel linear iterative solvers. The mapping of a topologically rectangular discrete grid onto a processor array of N × M transputers leads to step-like behaviour in the local communication and calculation time. This results in a typical oscillatory behaviour of ‘speed-up’ when problem sizes are increased monotonously. The theory is compared with experimental results obtained on a Parsytec Super Cluster Model 64 using a black-red SOR algorithm coded in 3L Parallel Fortran.
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