Speed-Area Optimized VLSI Architecture of Hexagonal Search Algorithm for Motion Estimation of $$512 \times 512$$ 512 × 512 Frames

Abstract

Motion estimation accounts for major part of the computational complexity of any video coding standard. In this paper, we present efficient VLSI architecture for the implementation of hexagonal search algorithm for fast motion estimation. The proposed architecture employs sequential processing of pixel data rather than parallel processing in order to reduce the hardware area substantially while achieving the real-time speed. A novel on-chip memory organization is proposed, which reduces the address generation complexity and helps improve the speed. The architecture when implemented in Verilog HDL and mapped to Virtex-5 FPGA achieves a maximum frequency of 340 MHz, while the gate count is calculated to be 3.1 K. Thus, the proposed architecture is considered suitable to be incorporated in commercial devices such as camcorders and smart phones.