Abstract
In this paper, a variety of adder and multiplier are compared to be implemented in a new logarithmic number system (LNS). Both adder and multiplier are designed with a generic very high-speed integrated circuit hardware description language (Verilog) program. This makes it possible to achieve the optimum performance in latency and area of 0.18µm CMOS technologies LNS chip. Consequently, the optimal configurations vary with speed and area of the schemes and in some cases can be compact area, O(n), fast in latency O(log2 n) or optimized. The program was scripted based on fixed-point (FXP) adders and multipliers that yet will be implemented in LNS system. The functionality of the scheme was tested before synthesized. Outcomes show that Ladner Fisher (LF) adder and modified Baugh Wooley multiplier contribute to fast in latency and consume minimal area.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IOP Conference Series: Materials Science and Engineering
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
