Specifics of Error Detection with Modular Sum Codes in Concurrent Error-Detection Circuits Based on Boolean Complement Method

Abstract

The authors of the paper analyze the specifics of error detection with modular sum codes which are found in synthesis of concurrent error-detection (CED) circuits based on the Boolean complement method. Errors in codewords of modular sum codes may not be detected by a checker if they occur only in data vectors and simultaneously in data and check vectors of the codewords, while errors in check vectors are always detected. In contrast to the previous studies in this subject area, the authors focus on the specifics of error detection by modular sum codes in all codewords, but not only in data vectors. Previously unknown properties of error detection by modular sum codes have been identified with their classification by types (unidirectional, symmetrical and asymmetrical errors) and multiplicities. The article describes in details modular sum codes, along with the key patterns inherent in this class of codes. The research results can be used in design of CED circuits based on Boolean complement method, or in other tasks of technical diagnostics where it is important to know the properties of error detection in codewords, as well as in tasks of data protection and transmission. The paper also provides an algorithm for synthesis of CED circuits for automation devices with known structures. In this case, circuit-oriented methods can be used to eliminate any errors that occur simultaneously in both data and check vectors of codewords.