Specification-based Verification of Embedded Systems by Automated Test Case Generation

Abstract

AbstractIt is time and resource intensive to derive test cases manually from the requirements specification to fully verify that the embedded system design fulfills its specification. However, automatic parsing to generate test cases is often not possible due to the informal, non-machine readable structure of the specification document. Formal specification languages would ease the parsing process, however they are difficult to use and rarely accepted. A promising trade-off are semi-formal specification languages, which are both easy-to-parse and easy-to-use.This paper presents a novel approach developed in the SIMBA1 project to tightly integrate a semi-formal requirements specification document into the design flow of embedded system designs. It considers the specification as a series of semiformal textual use cases and automatically generates specification-based SystemC test cases. During a simulation with the System-under-Verification (SuV) the test cases are executed to determine whether the SuV fulfills the specification. A demonstration is given by a case study of an RFID controller. It shows that errors in the specification and discrepancies between the design and its specification are detected.KeywordsSyntax TreePlatform GeneratorSouth African InstituteTest Case SelectionEmbed System DesignThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.