Abstract
For controller synthesis to be successful, detailed knowledge of the timing constraints of the system under synthesis is essential. The authors present a method for extracting timing constraints from a behavioral description, architectural restrictions, component timing requirements and protocol specifications. The timing constraints are combined in a timing constraint graph that can be solved in polynomial time using algorithms known from symbolic layout compaction. >
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
