Specializing for Efficiency: Customizing AI Inference Processors on FPGAs

Abstract

Artificial intelligence (AI) has become an essential component in modern datacenter applications. The high computational complexity of AI algorithms and the stringent latency constraints for datacenter workloads necessitate the use of efficient specialized AI accelerators. However, the rapid changes in state-of-the-art AI algorithms as well as their varying compute and memory demands challenge accelerator deployments in datacenters as a result of the much slower hardware development cycle. To this end, field-programmable gate arrays (FPGAs) offer the necessary adaptability along with the desired custom hardware efficiency. However, FPGA design is non-trivial; it requires deep hardware expertise and suffers from long compile and debug times, making FPGAs difficult to use for software-oriented AI application developers. AI inference soft processor overlays address this by allowing application developers to write their AI algorithms in a high-level programming language, which are then compiled into instructions to be executed on an AI-targeted soft processor implemented on the FPGA. While the generality of such overlays can eliminate the long bitstream compile times and make FPGAs more accessible for application developers, some classes of the target workloads do not fully utilize the overlay resources resulting in sub-optimal efficiency. In this paper, we investigate the trade-off between hardware efficiency and designer productivity by quantifying the gains and costs of specializing overlays for different classes of AI workloads. We show that per-workload specialized variants of the neural processing unit (NPU), a state-of-the-art AI inference overlay, can achieve up to 41% better performance and 44% area savings.