SPC Pixel IC with 9.4 e− rms Offset Spread, 60 e− rms ENC and 70 kfps Frame Rate

Abstract

We report on design and measurements of the integrated circuit in CMOS 130 nm for readout of hybrid pixel detector operating in a single photon counting (SPC) mode. A core of IC contains a matrix of 128 × 176 square shaped pixels of 75 µm pitch. Each readout pixel consists of charge sensitive amplifier (CSA), shaper, two discriminators and two 14-bit counters. The novel CSA feedback, with the effective resistance of 0.6 GΩ and sets of switches, allows for sensor leakage current compensation up to tens of nA, fast return to the CSA output baseline even in the case of the high frequency of input pulses, and low noise operation. The measured equivalent noise charge is only 60 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> rms, while an offset spread is 9.4 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> rms. These parameters allow to count and distinguish photons in each pixel independently, even if the difference between photons’ energies is only 0.86 keV. Having in mind future synchrotron applications, the several readout schemes of the pixel matrix are implemented. The continuous readout mode allows for 70 kfps frame rate. The power consumption per single pixel is about 37 µW.