Spatial retardation of carrier heating in scaled 0.1-μm n-MOSFET's using Monte Carlo simulations

Abstract

A comprehensive Monte Carlo simulator is employed to investigate nonlocal carrier transport in 0.1 /spl mu/m n-MOSFET's under low-voltage stress. Specifically, the role of electron-electron (e-e) interactions on hot electron injection is explored for two emerging device designs biased at a drain voltage V/sub d/ considerably less than the Si/SiO/sub 2/ injection barrier height /spl phi//sub b/. Simulation of both devices reveal that 1) although qV/sub d/</spl phi//sub b/, carriers can obtain energies greater than /spl phi//sub b/, and 2) the peak for electron injection is displaced approximately 20 nm beyond the peak in the parallel channel electric field. These phenomena constitute a spatial retardation of carrier heating that is strongly influenced by e-e interactions near the drain edge. (Virtually no injection is observed in our simulations when e-e scattering is not considered.) Simulations also show that an aggressive design based on larger dopant atoms, steeper doping gradients, and a self-aligned junction counter-doping process produces a higher peak in the channel electric field, a hotter carrier energy distribution, and a greater total electron injection rate into the oxide when compared to a more conventionally-doped design. The impact of spatially retarded carrier heating on hot-electron-induced device degradation is further examined by coupling an interface state distribution obtained from Monte Carlo simulations with a drift-diffusion simulator. Because of retarded carrier heating, the interface states are mainly generated further over the drain region where interface charge produces minimal degradation. Thus, surprisingly, both 0.1 /spl mu/m n-MOSFET designs exhibit comparable drain current degradation rates.