Spatial Degradation Profiling Technique in Self-Aligned Top-Gate a-InGaZnO TFTs Under Current-Flowing Stress

Abstract

An analysis technique of quantitatively extrac- ting the spatial profile of the channel characteristics is proposed and utilized to observe the local electrical degradation in amorphous InGaZnO (a-IGZO) TFTs. Device degradation is observed by current–voltage and capacitance–voltage characteristics after applying stress with different gate ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\textit {GS}}$ </tex-math></inline-formula> ) and drain biases ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\textit {DS}}$ </tex-math></inline-formula> ) considering operation conditions. The asymmetry of device degradation becomes severe as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\textit {DS}}$ </tex-math></inline-formula> for stress condition increases. In addition, after applying stress with the largest <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\textit {DS}}$ </tex-math></inline-formula> , a hump resulting from different types of degradation depending on location was observed: donor creation ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${2.5} \times {10}^{{18}}$ </tex-math></inline-formula> eV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-{1}}$ </tex-math></inline-formula> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-{3}}$ </tex-math></inline-formula> ) near drain and electron trapping ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${2} \times {10}^{{12}}$ </tex-math></inline-formula> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-{2}}$ </tex-math></inline-formula> ) into gate insulator near source. The spatial profiling technique can be utilized as a quantitative analysis tool for stable TFT and circuit design for the various applications of displays.