Abstract
Problem statement: The image processing applications, such as MPEG video compression used in CT scan frames requires real time conditions and the algorithms should be verified and optimized before implementation which cannot be done with Application Specific Integrated Circuits (ASICs) because they are not reconfigurable and cost is very high. Approach: The FPGA is a viable technology that could be implemented and reconfigured at the same time, since FPGA have the benefit of hardware speed and the flexibility of software. Results: The results obtained from Sparatn-3An FPGA show that the mean delay time for four multipliers, clearly indicates as the size of multiplier increases the mean delay time also increases. Conclusion: The FPGA based truncated multipliers could also be used in medical imaging technology.
Highlights
To date, many research efforts have been presentedDigital Signal Processing (DSP) requires intensive scientific computations for real time imaging processes
Truncated multipliers do not form all of the leastsignificant columns in the partial-product matrix as Architecture platform: Due to the parallel nature, high frequency and high density of modern Field Programmable Gate Arrays (FPGAs), they make an ideal platform for the implementation of computationally intensive and massively parallel architecture
The family consists of eight member offering densities ranging from 50,000 to five million system gates (Xilinx, 2008) The Spartan-3 FPGA consists of five fundamental programmable functional elements: CLBs, IOBs, Block RAMs, dedicated multipliers (18×18) and digital clock managers (DCMs), Spartan-3 family includes Spartan3L, Spartan-3E, Spartan-3A, Spartan-3A DSP, Spartan3AN and the extended Spartan-3A FPGAs
Summary
Digital Signal Processing (DSP) requires intensive scientific computations for real time imaging processes. The multipliers play a crucial role in such delicates and important computations. Implementation of DSP algorithm demands using Application Specific Integrated Circuits (ASICs). The in literature to achieve hardware efficient implementation of a truncated multiplier (Rais, 2009a; 2009b; Rais, 2010a). A hardware design and implementation of FPGA based parallel architecture for standard and truncated multipliers is presented. The Field Programmable Gate Arrays (FPGAs) have emerged as a platform of choice for efficient hardware implementation of computation intensive algorithms. Truncated multiplication provides an efficient method for reducing the power dissipation and area of rounded parallel multiplier (Rais, 2010b). Factors that play an important role in FPGA based design are the targeted FPGA architecture, Electronic Design
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