Abstract

This paper introduces sparse random signals for fast convergence on invertible logic. Invertible logic based on a network of probabilistic nodes (spins), similar to a Boltzmann machine, can compute functions bidirectionally by reducing the network energy to the global minimum with the addition of random signals. Here, we propose using sparse random signals that are generated by replacing a part of the typical dense random signals with zero values in probability. The sparsity of the random signals can induce a relatively relaxed transition of the spin network, reaching the global minimum energy at high probabilities. As a typical design example of invertible logic, invertible adders and multipliers are designed and evaluated. The simulation results show that the convergence speed with the proposed sparse random signals is roughly an order of magnitude faster than that with the conventional dense random signals. In addition, several key parameters are found and could be a guideline for fast convergence on general invertible logic.

Highlights

  • Invertible logic has recently been presented for providing the capability of forward and backward operations [1] as opposed to typical binary logic for only the forward operation

  • The increase in I0 is iteratively applied from I0min to I0max until the maximum cycle (Tmax ), where the number of iterations (Niter ) is Tmax /Titer

  • In this paper, three sparse random signals are presented for fast convergence on invertible logic

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Summary

Introduction

Invertible logic has recently been presented for providing the capability of forward and backward operations [1] as opposed to typical binary logic for only the forward operation. It is designed based on underlying Boltzmann machines [2] realized by a network of probabilistic nodes (spins), where the spin states are represented by random streams of ‘‘−1’’ and ‘‘1’’. Invertible logic was originally realized using probabilistic device models that were later implemented using CMOS digital circuits with binary logic [5] and stochastic computing [6].

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