SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems

Abstract

With the size of modern VLSI circuits growing in size to billions of transistors, multi-FPGA systems have been widely applied in circuit emulation and prototyping. To make full advantage of limited FPGA resources and improve the system frequency, designing a flexible multi-FPGA system with a corresponding design compilation flow is an important research problem in both industry and academia. In this work, we propose a practical and scalable partitioning and routing framework, named SPARK, for a multi-FPGA system with an adjustable near-square mesh shape and the minimum number of FPGAs. To resolve the significant constraints on multiple hardware resources for partitioning, SPARK leverages the general hypergraph partitioning tool by combining it with an efficient legalization algorithm to minimize cut size without resource overflow. We also propose novel max_cut-driven maze routing and max_hop-driven refinement algorithms to optimize the max_cut and max_hop in multi-FPGA systems meanwhile and improve the system frequency. Extensive experiments using the largest public circuit benchmarks for FPGA and several small FPGA settings from the industry demonstrate the effectiveness and efficiency of SPARK.