Spacer engineering for performance enhancement of junctionless accumulation‐mode bulk FinFETs

Abstract

This study investigates the performance of the junctionless accumulation-mode (JAM) bulk FinFETs. Different electrical parameters are simulated and analysed for the device with different gate spacer's lengths and materials. Spacers having dielectric constants between 1 and 22 are used to compare the device performance, whereas different spacer lengths are considered in order to understand the effect of spacer engineering. Importance is given to investigate the analogue and radio frequency (RF) performances by computing transconductance ( g m ), transconductance generation factor ( g m / I d ), cut-off frequency ( f T ), maximum frequency of oscillation ( f max ) and so on. The device under study shows better ON-OFF current ratio, transconductance, transconductance generation factor using gate spacer having high k -value. However, because of increased gate capacitances, its RF performance degrades with increase in dielectric constant of the spacer used. The effects of downscaling of channel length ( L ) on analogue performance of the proposed junctionless accumulation mode device have also been presented. It has been observed that the analogue/RF performance of the device can be improved by reducing the spacer length.