Spacer defined double patterning for (sub-)20nm half pitch single damascene structures

Abstract

The spacer defined double patterning (SDDP) approach for 20nm half pitch (HP) single damascene Cu interconnect structures using immersion lithography is being reviewed. Final results on wafer will be shown, focusing on critical double patterning topics such as CD & overlay budget and line edge roughness (LER); and their impact on the electrical functioning of the back-end-of-line test structures. The feasibility of extending the SDDP technique down to 15nm HP structures is also discussed. The 30nm line/space structures patterned in resist, required as a starting point for this exercise, will be patterned using EUV lithography.