Spacer and material engineered performance enhancement of FinFET with polygonal epitaxi

Abstract

The performance of planar MOSFETs is limited by short-channel effects (SCE). To overcome SCE, FinFETs which are a type of multigate FETs, have been adopted for mass production. This structure allows more gate control than planar MOSFETs provide, but they have higher source/drain (S/D) parasitic resistance. Number of methods have been made to reduce the S/D resistance. In this work we introduce a new compact model of the parasitic resistance of a FinFET with polygonal source–drain (S/D) structure. In contrast to previous models, we redefined the region boundaries and modeled them as a series connection of accumulation resistance, gradient resistance, and contact resistance. It significantly improved the contact resistance model to reflect the contact area and contact resistivity for better accuracy in the raised S/D region. We validated the accuracy of our model by varying the doping diffusion length and contact resistivity. The epitaxial layer is fabricated using materials such as Si, Ge and SiGe. For better performance different spacer materials are used. A significant reduction in parasitic S/D resistance is obtained by SiGe as the epitaxial layer with high-k dielectric HfO2 as spacer on both sides of source and drain. The tool used for simulation is Silvaco TCAD and MATLAB. Heterojunctions can be used for enhancing the device performance.