Space-memory-memory architecture for CLOS-network packet switches

Abstract

A Clos-network architecture is an attractive alternative for constructing scalable packet switches because of its distributed and modular design. It can be classified according to different buffer (memory) allocation schemes in its switching stages. The most studied architectures are the space-space-space (S3) and the memory-space-memory (MSM) architectures. This paper shows that these two architectures cannot achieve efficient throughput with conventional random dispatching schemes even if the fabric itself is non-blocking. Previous research hence has focused on developing intelligent scheduling algorithms for these architectures so as to improve their throughput. However, we face various challenging problems when we try to actually implement the algorithms. The problems include performance degradation under constrained arbitration time, needs of centralized or complex scheduler hardware, etc. To solve these problems and at the same time be practical, this paper proposes a novel space-memory-memory (SMM) architecture that does not need any schedulers. The SMM architecture has similar hardware complexity as the MSM architecture has, while been proven to achieve 100% throughput under any admissible traffic. Our queuing analysis demonstrates that only small size buffers are needed in the central stage. The only tradeoff for the proposed SMM architecture is to employ small extra resequencing buffers. As a result, the SMM architecture can achieve very high performance, and is readily implemented using current technology.