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Abstract
Resistive switching through electroresistance (ER) effect in metal-ferroelectric-metal (MFM) capacitors has attracted increasing interest due to its potential applications as memories and logic devices. However, the detailed electronic mechanisms resulting in large ER when polarisation switching occurs in the ferroelectric barrier are still not well understood. Here, ER effect up to 1000% at room temperature is demonstrated in C-MOS compatible MFM nanocapacitors with a 8.8 nm-thick poly(vinylidene fluoride) (PVDF) homopolymer ferroelectric, which is very promising for silicon industry integration. Most remarkably, using theory developed for metal-semiconductor rectifying contacts, we derive an analytical expression for the variation of interfacial barrier heights due to space-charge effect that can interpret the observed ER response. We extend this space-charge model, related to the release of trapped charges by defects, to MFM structures made of ferroelectric oxides. This space-charge model provides a simple and straightforward tool to understand recent unusual reports. Finally, this work suggests that defect-engineering could be an original and efficient route for tuning the space-charge effect and thus the ER performances in future electronic devices.
Highlights
Research on resistive switching in metal-ferroelectric-metal (MFM) capacitors has been intensified recently due to its potential applications in the generation of non-volatile memories and logic devices[1,2,3,4]
By studying the ER effect in MFM structures based on 8.8-nm thick ferroelectric poly(vinylidene fluoride) [PVDF, -(CH2-CF2)n-], we reveal that unusual energy profiles at interfaces can be understood using a simple space-charge mechanism
Resistive switching depending on the orientation of the polarisation in organic MFM capacitors has been observed with an ON/OFF ratio of about 10–100%17–21
Summary
Research on resistive switching in metal-ferroelectric-metal (MFM) capacitors has been intensified recently due to its potential applications in the generation of non-volatile memories and logic devices[1,2,3,4]. For a ferroelectric material sandwiched between two different metallic electrodes, the typical energy profiles due to the incomplete screening are depicted in Fig. 1a: the two polarization states (pointing to the left or to the right) correspond to different average barrier heights This imperfect screening is affected by interfacial effects which can be ascribed to defect-free layers having a different polarisation from that of the ferroelectric core and/ or so-called dead-layers originating from non-switchable interface defects or pinned dipoles[9,10,11]. These MFM structures are integrated onto silicon substrate and are C-MOS compatible, opening the route for future applications
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