Abstract
AbstractTiling is a well‐known technique for sequential compiler optimization, as well as for automatic program parallelization. However, in the context of parallelization, tiling should not be considered as a stand‐alone technique, but should be applied after a dedicated parallelization phase, in our case after space–time mapping. We show how tiling can benefit from space–time mapping, and we derive an algorithm for computing tiles which can minimize the number of communication startups, taking the number of physically available processors into account. We also present how the use of a simple cost model reduces real execution time. Copyright © 2004 John Wiley & Sons, Ltd.
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