Abstract
In Chapter 2, different SRAM models have been discussed; e.g., the functional model, which is the collection of the functional specifications of the memory together with the internal structure of its subsystems. In general, the functional model of a memory depends on its specific implementation. However, for test purposes a so called ‘reduced functional memory model’ is used that only consists of three subsystems: the address decoder, the memory cell array and the read/write logic. Since the vast majority of mainstream memory devices contains these three subsystems, the reduced functional fault model is, to a large extent, independent of specific memory implementations.
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