Abstract

The source/drain (S/D) series resistance of nanoscale ultra-thin-body (UTB) SOI MOSFETs with elevated S/D structure and undoped or very-low-doped channel regions is studied with a device simulator. The dependences of the series resistance and its components on the device geometry/process parameters are quantitatively investigated. It is shown that the S/D contact resistivity, S/D extension length and S/D doping profile are the major factors determining the series resistance. A number of guidelines for designing nanoscale UTB devices are suggested on the basis of the simulated results. Moreover, it is implied that the conventional S/D doping approach, namely gate-S/D overlap doping, is very unlikely to be competent for sub-50 nm technology applications because it results in an unacceptably large series resistance and poor short-channel performance. A new S/D doping scheme called gate to S/D underlap doping is proposed and studied. Results indicate that the new doping approach can help with scaling UTB devices into 18 nm technology node and below.

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