Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node

Jun-Sik Yoon,Hyeok Yun,Bohyeon Kang,Jinsu Jeong,Rock-Hyun Baek,Junjong Lee,Seunghwan Lee

doi:10.1109/access.2019.2956503

Abstract

A novel and feasible process scheme to downsize the source/drain (S/D) epitaxy of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) were introduced by using fully-calibrated TCAD for the first time. The S/D epitaxy formed by selective epitaxial growth was diamond-shaped and occupied a large proportion of the device size irrespective of the active channel area. However, this problem was solved by patterning the low-k regions prior to S/D formation by preventing the lateral overgrowth of S/D epitaxy; the so-called S/D patterning (SDP). Its smaller S/D epitaxy decreased the average longitudinal channel stresses and drive currents for NFETs. However, the small diffusions of the boron dopants into the channel regions improved the short-channel effects and alleviated the drive current reduction for PFETs. Gate capacitances decreased greatly by reducing outer-fringing capacitances between the metal-gate stack and S/D regions. Through SPICE simulation based on the virtual source model, operation frequencies and dynamic powers of 15-stage ring oscillators were studied. SDP FinFETs have better circuit performances than the conventional and bottom oxide bulk FinFETs along with smaller active areas, promising for further area scaling through simple and reliable S/D process.

Highlights

Si fin-shaped field-effect transistors (FinFETs) have been scaled down to 10-nm node [1] by optimizing fin channels and layouts to increase the gate-to-channel controllability and device density, respectively
As the device advanced to bottom oxide (BO) and S/D patterning (SDP), both the Subthreshold swing (SS) and drain-induced barrier lowering (DIBL) decreased, and the Vth increased for PFETs, whereas similar SCEs are shown for NFETs
Smaller amounts of boron dopants diffuse into the active channel regions for the p-type SDP FinFETs, which improved the SCEs

Summary

Introduction

Si fin-shaped field-effect transistors (FinFETs) have been scaled down to 10-nm node [1] by optimizing fin channels and layouts to increase the gate-to-channel controllability and device density, respectively. As the device advanced to BO and SDP, both the SS and DIBL decreased, and the Vth increased for PFETs, whereas similar SCEs are shown for NFETs. This effect is explained by S/D doping profiles (Fig. 3b). Smaller amounts of boron dopants diffuse into the active channel regions for the p-type SDP FinFETs, which improved the SCEs. SDP FinFETs without BO are included, showing that the PFETs suffer from the punch-through effect at the bottom fin.

Results

Conclusion