Abstract
A circuit for handling pulse width modulation (PWM) first signal and PWM second signal for outputting to an amplifier, the PWM first signal having one of a same phase and an opposite phase relationship with the PWM second signal, the circuit comprising a power detector for detecting power turn on to the amplifier and outputting a power on signal and detecting a power turn off to the amplifier and outputting a power off signal; a pulse generator having: a duty cycle generator for generating a first pulse signal corresponding to the PWM first signal and a second pulse signal corresponding to the PWM second signal, and a reduced-width generator for generating at least one of a reduced-width first pulse and a reduced-width second pulse; a controller for selecting one of the reduced-width first pulse and the reduced-width second pulse for outputting to the amplifier upon receipt of the power on signal and for selecting the first pulse signal and the second pulse signal for outputting to the amplifier thereafter; and a counter for counting the duration of the pulse width of the PWM first signal, the counter being activated upon detection of the power off signal and a select circuit for outputting an off select signal upon reaching a predetermined reduced-width time count to cause an output of one of a reduced-width PWM first signal and a reduced-width PWM second signal.
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