Some VLSI decompositions of the de Bruijn graph

Abstract

We define a VLSI decomposition of a directed graph G to be a collection of isomorphic vertex-disjoint subgraphs of G which together contain all of G's vertices. We call the isomorphic subgraphs comprising the decomposition building blocks for the graph G, and we refer to the edges contained in the collection of subgraphs as internal edges. The efficiency of a VLSI decomposition of G is the fraction of the total number of edges in G which are internal edges. In this paper we will present a general construction for efficient VLSI decompositions for the family of de Bruijn graphs. Using the methods to be explained in this paper, we have found a 64-chip VLSI decomposition of the de Bruijn graph B 13 with efficiency 0.754, which is being used by JPL design engineers to build a single-board Viterbi decoder for the K = 15, rate 1 4 convolutional code which will be used on NASA's Galileo mission.