Some Transport Issues in the Development, Qualification, and Manufacture of Electronic Packages

Abstract

Abstract There are significant transport issues that arise in the development, assembly, qualification, and manufacturing of organic packages. These issues include diverse areas like chemical processing of printed wiring boards (PWBs) during etching, plating and rinsing, lamination of cores, drilling of plated through holes, profiling (the separation of individual chip carriers or PWBs from a large panel) and adhesive curing, all of which occur during the manufacturing of the PWBs and chip carriers. During assembly and rework, transport issues arise in solder reflow during module attach and re-work, adhesive cure during heat-sink attach, and under-fill and curing processes in flip chip packages. Similar, but more complex, processes are encountered in wafer level packaging. During reliability stress testing, concerns arise about establishment of appropriate stress and acceleration factors that relate the accelerated tests to actual field conditions. During shipping and handling, similar concerns arise in simulating potential temperature excursions that may occur. In addition to these thermal and transport issues, manufacturing processes may induce interfacial de-lamination due to surface conditions resulting from process history, residual stresses in the package that impact the thermal performance of the package and manufacturing tolerances that inherently affect the thermal performance. Additionally, ever reducing time-to-market demands novel methods of package manufacture and reliability qualification. Experimentally validated modeling and simulation must play an important role towards this goal. The methodologies and tools must continuously be upgraded to achieve true concurrent engineering. In spite of the wide spread use of numerical simulation, there is much that remains to be done to make simulation truly useful to the practicing engineer in the electronics cooling and packaging area. Among the important shortcomings are: (i) restriction to disciplinary boundaries — electronics cooling and packaging is inherently interdisciplinary, but nearly all simulation tools are discipline-specific; (ii) an emphasis on analysis rather than on synthesis — there are few tools to translate insights from detailed component-level simulations into a broader systemic view; and (iii) long lead times and, consequently, an inability to impact the short time-scale design processes inherent to the electronics manufacturing/ packaging area. The purpose of this panel session is to initiate discussion and idea exchange related to some of these topics. The tone of the panel is set by presentations by panelists addressing the technology aspects of packaging, processes and materials covering three broad issues: substrates, assembly and system-level packaging. The emerging technology challenges in each of these areas will be addressed with attendant examples mainly from computer, automotive electronics. Technology roadmaps will be discussed with special reference to the needs of the automotive electronics of the future. These needs will be translated into the required technology solutions in the substrate, assembly, and packaging arenas. The presentations will also identify future areas of research in modeling and simulation that address the technology broadly related to the technology needs identified above. Such modeling and simulation topics are multi-disciplinary in nature enveloping design, materials selection, and manufacturability. While these topics are of great interest to industry from a concurrent engineering point of view, they also present a great challenge to the academic community to integrate multi-disciplinary nature of this problem and develop truly predictive methods and tools for pervasive use in the industry. The panelists are a combination of industrial and academic researchers as can be seen from their attached biographies below and they will share their vision for long term resolution of this vision.