Abstract
A full understanding of the physics and statistics of the defect generation is required to investigate the ultimate reliability limitations of manufacturability of MEMS and NEMS. In order that the user can include electronic components in circuits to achieve errorfree and reliable functional units, assemblies or devices, must he has understood the mode of operation of these components. Only knowledge of their parameters and special properties allows, according to data sheet specifications and manufacturer's documents the optimal components for a specific application, to select. Both for the analysis of electronic circuits and for circuit dimensioning are knowledge of the structure and function of the used components of semiconductor electronics absolutely necessary.
Highlights
An failure mode (FMo) is the external symptom of the failed product: for example, a bipolar (Bi) transistor has a short circuit between emitter and collector
failure mechanism (FM) identification is essential for the reliability of accelerated testing because: – FMs produced by high-level stress cannot be different to those observed during actual service conditions; – The obtained degradation laws must be extrapolated beyond the time period of the test and the extrapolation must be made separately for each population affected by an FM
Wafer Level There are two reasons why wafer is the favourite target for failure analysis (FA): (i) many interesting physical and chemical phenomena are involved in component degradation and failure and (ii) the wafer is a collection of reliability risks, almost any process step may induce a new FM or increase the action of FMs induced by previous steps
Summary
An failure mode (FMo) is the external symptom of the failed product: for example, a bipolar (Bi) transistor has a short circuit between emitter and collector. Wafer Level There are two reasons why wafer is the favourite target for FA: (i) many interesting physical and chemical phenomena are involved in component degradation and failure and (ii) the wafer is a collection of reliability risks, almost any process step may induce a new FM or increase the action of FMs induced by previous steps. This is why a huge quantity of literature has been written on this subject and various techniques for waferlevel FA have been developed. The non-uniformity of the resistivity across the wafer is a failure risk, because the characteristics of the devices may differ depending on the area of the wafer
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