Some practical issues in the design and application of a VLSI FEC chip

Abstract

AbstractForward error correction (FEC) has become a general requirement for digital satellite communications. The dominant technology is the use of convolutional codes with Viterbi decoding. At MPR (Microtel Pacific Research), a single‐chip VLSI implementation of a convolutional encoder and Viterbi decoder for constraint length 7 has been completed recently. In the design and application of the FEC chip, several practical issues had to be addressed. These include the determination of the maximum variation in path metric, generation of a convolutional encoded sequence with maximum number of transitions for symbol timing recovery, use of a unique word to detect the phase ambiguity, use of a sliding window data quality monitor to resolve an ambiguous state, etc. This paper presents our solutions to these problems. Although specific results are given for the standard constraint‐length 7 code, the methods used to obtain these results are general and can be applied to other codes. Features and implementation of the VLSI FEC chip are also discussed.