Abstract
This paper studies the test pattern generation problem for FPGA implemented combinational circuits. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of manufacturing-oriented test procedure, application-oriented test procedure and AC-non-redundant fault. Then, the test pattern generation problem is discussed and it is pointed out that a high AC-non-redundant fault coverage can be obtained only by using an adequate FPGA representation. It is also shown that test pattern generation performed on the FPGA representation can be significantly accelerated by different techniques. A procedure called TOF is described to validate the proposed approach on benchmark circuits.
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