Abstract
The exceptionally large thermal strain in few-micrometers-thick 3C-SiC films on Si(111), causing severe wafer bending and cracking, is demonstrated to be elastically quenched by substrate patterning in finite arrays of Si micro-pillars, sufficiently large in aspect ratio to allow for lateral pillar tilting, both by simulations and by preliminary experiments. In suspended SiC patches, the mechanical problem is addressed by finite element method: both the strain relaxation and the wafer curvature are calculated at different pillar height, array size, and film thickness. Patches as large as required by power electronic devices (500–1000 μm in size) show a remarkable residual strain in the central area, unless the pillar aspect ratio is made sufficiently large to allow peripheral pillars to accommodate the full film retraction. A sublinear relationship between the pillar aspect ratio and the patch size, guaranteeing a minimal curvature radius, as required for wafer processing and micro-crack prevention, is shown to be valid for any heteroepitaxial system.
Highlights
In Ref. 1, a new architecture for exceptionally efficient compliant substrates in the epitaxial growth of severalmicrons-thick Ge layers on Si (001) is proposed
Merging of the Ge crystals into a suspended Ge patch on the pillar array was obtained and theoretically analyzed, both by subsequent and prolonged thermal annealing,4 or by growth at higher temperatures
III A, we focused on the mechanism of thermal strain relaxation made possible by exploiting the Si pillar architecture, just considering a SiC film with a thickness of 8 lm
Summary
In Ref. 1, a new architecture for exceptionally efficient compliant substrates in the epitaxial growth of severalmicrons-thick Ge layers on Si (001) is proposed. Subsequent Ge deposition by low energy plasma enhanced chemical vapor deposition provides selfaligned prismatic Ge crystals on the Si pillar top, spaced a few hundreds of nanometers for a vertical growth lasting tens of micrometers.. Merging of the Ge crystals into a suspended Ge patch on the pillar array was obtained and theoretically analyzed, both by subsequent and prolonged thermal annealing, or by growth at higher temperatures.. Merging of the Ge crystals into a suspended Ge patch on the pillar array was obtained and theoretically analyzed, both by subsequent and prolonged thermal annealing, or by growth at higher temperatures.5 The principle of such an approach was proven for standard Ge deposition in a thermal CVD apparatus and for cubic 3C-SiC/Si (001) and (111).. Subsequent Ge deposition by low energy plasma enhanced chemical vapor deposition provides selfaligned prismatic Ge crystals on the Si pillar top, spaced a few hundreds of nanometers for a vertical growth lasting tens of micrometers. Merging of the Ge crystals into a suspended Ge patch on the pillar array was obtained and theoretically analyzed, both by subsequent and prolonged thermal annealing, or by growth at higher temperatures. The principle of such an approach was proven for standard Ge deposition in a thermal CVD apparatus and for cubic 3C-SiC/Si (001) and (111). Heteroepitaxial growth on Si pillars was demonstrated for other systems, e.g., GaAs/Si10 and GaAs/Ge/Si11 or GaN/Si.
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