Solution-Based Fabrication of P-Channel and N-Channel Thin-Film Transistors Using Random and Aligned Carbon Nanotube Networks

Abstract

Since discovered in the early 1990s, single-walled carbon nanotubes (SWNTs) have attracted significant attention for many research fields. In the long term, micro- and nano-electronics are considered to be one of the most valuable applications of SWNTs. The development of the next generation devices involves the mass fabrication and integration of SWNT field-effect transistors (FETs) to form logic gates, which are the basic units of integrated circuits (ICs). To create logic gates, both p- and n-type SWNT FETs are needed. However, the SWNT FETs are typically p-type in air without special treatment, with holes as the majority charge carriers in SWNTs. Here in this paper, we investigate the p-channel and n-channel SWNT FETs using two solution-based fabrication processes. One method is to use layer-by-layer self-assembly to create SWNT random networks and the other is based on dielectrophoresis-aligned SWNTs. A low-cost, easy-to-control method is introduced to convert p-type FETs to n-type. By coating a polyethylenimine (PEI) layer on the surface, the transistor demonstrates the typical n-channel characteristics. The resulting devices are air-stable outside a vacuum or an inert environment. The combination of the simple fabrication methods, easy conversion of the devices, and satisfactory device performance can promote further development of nanotube-based electronics.