Abstract
We fabricated Si Quantum Dot (QD) devices using relatively minor adaptations of a standard SOI CMOS process flow. We demonstrated that the spin of confined charges could be controlled via a local electrical-field excitation, owing in the caseof electrons to a geometrically-enabled tuning of the valley splitting and inter-valley spin-orbit coupling. We discuss improvement paths such as extending the spin coherence time by using epi-layers of nuclear-spin-free 28Si (99.992%) as a device template, and developing novel 3D architectures compatible with topological quantum error correction schemes.
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