Software-Defined Radio design based on GALS architecture for FPGAs

Abstract

The design, implementation and comparison of Software-Defined Radio (SDR) based on GALS architectures were focused on. GALS port controllers, previously proposed for implementation in ASIC, have been redesigned for use in conventional FPGAs, eliminating the need for hard macros. A GALS architecture for SDR was proposed and validated, comprising a wrapper described in VHDL. In addition, some guidelines for its implementation in synchronous designs are shown. Whereas asynchronous wrappers were designed to be robust and to dispense timing verification, the verification effort is negligible, since the same test benches can be used for both designs. When compared with a synchronous design, a reduction of 39% in the dynamic consumption was obtained, what may be even greater if the idle clock periods are considered. We saw that for the same device, it is possible to earn 53% in the data flow (throughput), signifying that the radio is able to process a broader band, or that the cost of equipment can be reduced, once it is possible to adopt a cheaper FPGA version with lower performance.