Abstract
A recent paper comparing five standard 32-bit backplane buses suggests that the VMEbus does not provide adequate mechanisms to support software transparent cache consistency schemes. Although VMEbus lacks specific mechanisms used by some known bus-based consistency schemes, this is not felt to be insuperable. To substantiate this claim, this paper presents an ownership-based cache consistency scheme for a tightly coupled multiprocessor system with private cache memories, organized around the VMEbus. This scheme makes use of user-defined address modifiers and an address broadcast mechanism of the VMEbus. Additionally, it requires the participation of main memory by using a tag bit per block in main memory. The scheme presented conforms to the VMEbus Revision C Standard.
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