Software Implementation of Plantlet Stream Cipher Using Verilog Hardware Description Language

Abstract

AbstractNowadays, use of resources like area, energy, or power is restricted. The fewer resources should be used as much as possible. Thus, there is a lot of scope for lightweight stream ciphers. In this paper, software implementation of plantlet stream cipher has been performed using Verilog hardware description language on the Xilinx ISE design suite. One approach to obtain a lightweight stream cipher is to store the cipher key in non-volatile memory. This cipher key is used not only for the initialization process but it is also used during the encryption/decryption process. Plantlet stream cipher was proposed to improve the design of sprout that has minimum area compared to all other stream ciphers. In this paper, plantlet stream cipher is compared with two other ciphers. It is also a secured stream cipher to overcome the time-memory-data attacks. The main application of plantlet stream cipher is for security and lightweight constrained devices. In the plantlet, a double-layer LFSR is used such that the area is minimized and an all-zero state is avoided.KeywordsStream cipherUltra-lightweightEEPROMeSTREAMKeystreamLFSRNLFSR