Abstract
A data driven computer WASMII which exploits dynamically reconfigurable FPGAs based on a virtual hardware has been developed. This paper presents a software system which automatically generates a configuration data for FPGAs used in the WASMII. In this system, an application program is edited as a dataflow graph with a user interface, and divided into a set of subgraphs each of them is corresponding to the configuration data of an FPGA chip. These subgraphs are translated into program modules described in a hardware description language called the SFL. From the SFL programs, a logic synthesis tool PARTHENON generates a net-list of logic circuits for the subgraphs. Finally, the net-list is translated again for the Xiliux's CAD system, and the configuration data is generated. Here, the ordinary differential equation solver is presented as an example, and the number of gates is evaluated.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
