Software and firmware co-development using high-level synthesis

N.P Ghanathe,Y Xia,A.D George,A Jyothishwara,D.E Acosta,A Madorsky,M.R Carver,M Hansen,H Lam

doi:10.1088/1748-0221/12/01/c01083

N.P Ghanathe, Y Xia + Show 7 more

Open Access

https://doi.org/10.1088/1748-0221/12/01/c01083

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Abstract

Accelerating trigger applications on FPGAs (using VHDL/Verilog) at the CMS experiment at CERN's Large Hadron Collider warrants consistency between each trigger firmware and its corresponding C++ model. This tedious and time consuming process of convergence is exacerbated during each upgrade study. High-level synthesis, with its promise of increased productivity and C++ design entry bridges this gap exceptionally well. This paper explores the “single source code” approach using Vivado-HLS tool for redeveloping the upgraded CMS Endcap Muon Level-1 Track finder (EMTF). Guidelines for tight latency control, optimal resource usage and compatibility with CMS software framework are outlined in this paper.

Highlights

Accelerating trigger applications on FPGAs at the CMS experiment at CERN’s Large Hadron Collider at CERN warrants consistency between each trigger firmware and its corresponding C++ model
Guidelines for tight latency control, optimal resource usage and compatibility with CMS software framework are outlined in this paper
Recent advancements in high-level synthesis (HLS) tools hold the promise of high productivity through the use of design entry in C++ that reduces the difficulty for developing and managing code complexity at the HDL level

Summary

High-level synthesis languages and tools

High-level synthesis holds considerable promise in mitigating the cost of firmware development. There are many HLS tools available today and the choice of any HLS tool depends on a broad set of criteria such as source language, ease of implementation, tool complexity, support for data types, verification, latency, and resource usage after synthesis. The key evaluation criteria for this project are good latency control, resource usage after synthesis, compatibility of the source code in CMSSW, and ease of verification. The Vivado HLS compiler synthesizes the RTL design by extracting the control and datapaths from the HLS code, and maps it to hardware by using scheduling and binding processes while considering the directives supplied by the user. A key attribute of Vivado HLS critical for this study is that the user can override the defaults of the HLS compilation process by adding directives (pragmas) to the developed code to satisfy performance and other requirements and thereby has excellent control over the synthesized RTL. The HLS code is compatible with CMSSW [5]

CMS Level-1 Endcap Muon Track Finder

Increased productivity and flexibility using HLS

Fine-grained control using HLS constructs

Latency control - Scheduling of functions and operations

Construction of a delay line

HLS code compatibility and performance comparison on CMSSW