Abstract
This paper presents the design methodology of an integrated power amplifier, and coins the methodology as a software routine: for a given set of power amplifier specifications and CMOS process parameters, the routine computes the passive component values for a Class-E based power amplifier. The routine includes the matching network for standard impedance loads. The program also provides its user with a spiral inductor calculator, which can be used to determine inductance and parasitic values for an integrated square planar spiral inductor. The same tool has the ability to extract a Simulation Program With Integrated Circuit Emphasis netlist of inductor geometry, which can be used in the post layout simulations of the power amplifier. Operation of the program was demonstrated by simulations in Austria Microsystems 0.35 μm single-supply process for a 10 dBm, 2.4 GHz power amplifier design.
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