Abstract
We present a method to estimate the power and energy consumption of an algorithm directly from the C program. Three models are involved: a model for the targeted processor (the power model), a model for the algorithm, and a model for the compiler (the prediction model). A functional-level power analysis is performed to obtain the power model. Five power models have been developed so far, for different architectures, from the simple RISC ARM7 to the very complex VLIW DSP TI C64. Important phenomena are taken into account, like cache misses, pipeline stalls, and internal/external memory accesses. The model for the algorithm expresses the algorithm's influence over the processor's activity. The prediction model represents the behavior of the compiler, and how it will allow the algorithm to use the processor's resources. The data mapping is considered at that stage. We have developed a tool, SoftExplorer, which performs estimation both at the C-level and the assembly level. Estimations are performed on real-life digital signal processing applications with average errors of% at the C-level and% at the assembly level. We present how SoftExplorer can be used to optimize the consumption of an application. We first show how to find the best data mapping for an algorithm. Then we demonstrate a method to choose the processor and its operating frequency in order to minimize the global energy consumption.
Highlights
Lowering the power consumption of today’s electronic devices is more than ever a crucial challenge
Architectural parameters depend on the processor configuration which is explicitly defined by the programmer
We have introduced a new method for estimating the power and energy consumption of a DSP application directly from the C program
Summary
Lowering the power consumption of today’s electronic devices is more than ever a crucial challenge. There are several methods to estimate a processor’s power consumption, which we find at different levels in the modelling and analysis tool flow in microprocessor design. The model proposed in SimplePower is limited to an in-order 5-stage pipelined datapath, with perfect cache—the energy consumed by the control unit and the clock generation and distribution is not considered Another approach is to evaluate the power consumption with an instruction-level power analysis (ILPA) [23]. Our estimation method relies on a power model of the targeted processor, elaborated during the model definition step This model definition is based on the functional-level power analysis (FLPA) of the processor’s architecture [29]. The place of data has a very strong impact on the consumption, and the designer is able to try and compare different data mappings with the help of our tool
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