Abstract
As CMOS process technology scales below 100nm, the amount of charge required to upset a gate or memory cell (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">crit</sub> ) is decreasing. Therefore, the probability that an energetic particle can generate enough charge to upset a circuit is increasing. Since these single event upsets do not damage the IC, they are called soft errors. With the proper detection and correction schemes, these particle induced soft errors can be mitigated in a way that does not impact the overall reliability of an electronic system. Since memory devices such as SRAM, DRAM and Flash comprise the largest gate counts in many designs, it is essential to understand their soft error mechanisms, characterize their soft error rates and develop effective mitigation techniques.
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